Intel Xeon Phi Coprocessor Architecture and Tools

Intel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers provides developers a comprehensive introduction and in-depth look at the Intel Xeon Phi coprocessor architecture and the corresponding parallel data structure tools and algorithms used in the various technical computing applications for which it is suitable. It also examines the source code-level optimizations that can be performed to exploit the powerful features of the processor.

Xeon Phi is at the heart of world’s fastest commercial supercomputer, which thanks to the massively parallel computing capabilities of Intel Xeon Phi processors coupled with Xeon Phi coprocessors attained 33.86 teraflops of benchmark performance in 2013. Extracting such stellar performance in real-world applications requires a sophisticated understanding of the complex interaction among hardware components, Xeon Phi cores, and the applications running on them.

In this book, Rezaur Rahman, an Intel leader in the development of the Xeon Phi coprocessor and the optimization of its applications, presents and details all the features of Xeon Phi core design that are relevant to the practice of application developers, such as its vector units, hardware multithreading, cache hierarchy, and host-to-coprocessor communication channels. Building on this foundation, he shows developers how to solve real-world technical computing problems by selecting, deploying, and optimizing the available algorithms and data structure alternatives matching Xeon Phi’s hardware characteristics. From Rahman’s practical descriptions and extensive code examples, the reader will gain a working knowledge of the Xeon Phi vector instruction set and the Xeon Phi microarchitecture whereby cores execute 512-bit instruction streams in parallel.

What you’ll learn

• How to calculate theoretical Gigaflops and bandwidth numbers on the hardware and measure them through code segment
• How to estimate latencies in fetching data from different cache hierarchies, including memory subsystems
• How to measure PCIe bus bandwidth between the host and coprocessor
• How to exploit power management and reliability features built into the hardware
• How to select and manipulate the best tools to tune particular Xeon Phi applications
• Algorithms and data structures for optimizing Xeon Phi performance
• Case studies of real-world Xeon Phi technical computing applications in molecular dynamics and financial simulations

Who this book is for

This book is for developers wishing to design and develop technical computing applications to achieve the highest performance available in the Intel Xeon Phi coprocessor hardware. It provides a solid base on the coprocessor architecture, as well as algorithm and data structure case studies for Xeon Phi coprocessor. The book may also be of interest to students and practitioners in computer engineering as a case study for massively parallel core microarchitecture of modern day processors.

Table of Contents

Part1: Hardware Foundation: Intel Xeon Phi Architecture
Chapter 1: Introduction to Xeon Phi Architecture
Chapter 2: Programming Xeon Phi
Chapter 3: Xeon Phi Vector Architecture and Instruction Set
Chapter 4: Xeon Phi Core Microarchitecture
Chapter 5: Xeon Phi Cache and Memory Subsystem
Chapter 6: Xeon Phi PCIe Bus Data Transfer and Power Management

Part2: Software Foundation: Intel Xeon Phi System Software and Tools
Chapter 7: Xeon Phi System Software
Chapter 8: Xeon Phi Application Development Tools

Part3: Applications: Technical Computing Software Development on Intel Xeon Phi
Chapter 9: Xeon Phi Application Design and Implementation Considerations
Chapter 10: Application Performance Tuning on Xeon Phi
Chapter 11: Algorithm and Data Structures for Xeon Phi
Chapter 12: Xeon Phi Application Development on Windows OS

Appendix A: OpenCL on Xeon Phi
Appendix B: Virtual Shared Memory Programming on Xeon Phi